About this opportunity
TSMC - Taiwan Semiconductor Manufacturing Company Limited lists this Advanced Physical Design & Verification Engineer – Hybrid opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
TSMC Technology, Inc. is seeking an Advanced Physical Design and Verification Engineer in San Jose, CA, to drive physical design checks and ECO-based timing closures.
The role involves DRC/LVS/EM analysis, floorplanning, and clock-tree customization in a hybrid work model with four days in office. The candidate should have a Master’s degree in electrical engineering or CS, strength in RTL, Python, and EDA tools, and a background in design verification or related internships.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.