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Job description
Architect Labs in California seeks a Senior RTL Design Engineer to own AI-driven microarchitectures for high-performance networking subsystems. You will drive Ethernet MAC/PCS blocks, TX/RX pipelines, and datapath integration into production silicon.
You'll collaborate with the architecture, DV, SW, and ML teams, define interface specs, and support FPGA prototyping on Xilinx platforms, ensuring protocol compliance and power-aware design choices.
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Worksite address
palo alto, CA, 94306, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.