About this opportunity
EDA CAREERS, (Technology Futures Inc). lists this AI-Driven UVM Verification Engineer opportunity in san francisco, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
An innovative startup at the forefront of AI and semiconductor design is seeking a Design Verification Engineer with expertise in UVM. This role offers the opportunity to work on cutting-edge technologies that automate chip development using AI. As part of a small, elite team, you will develop and deploy UVM testbenches, collaborating closely with machine learning and software engineers. This position is perfect for those eager to explore AI-integrated semiconductor design and make a significant impact in the industry. Join a mission-driven team that is reshaping the future of chip verification and development.
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Worksite address
san francisco, CA, 94199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.