About this opportunity
Conductor lists this ASIC Design Engineer - Multi-Die & AI Chips opportunity in boston, Massachusetts. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Conductor is seeking ASIC design engineers to contribute to and own blocks in the A-0 and A-1 wafer products, spanning XPU, memory chiplet and other dies on the wafer.
You will drive design ownership, optimize PPA, and iterate rapidly across multiple advanced node tapeouts, applying creative methodologies to accelerate development and improve performance.
Strong candidates will demonstrate hands-on tapeouts and end-to-end block ownership across complex die architectures.
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Worksite address
boston, MA, 02298, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.