About this opportunity
NVIDIA Corporation lists this ASIC Design Engineer - New College Grad 2026 opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full timeposted on: Posted 2 Days Agojob requisition id: JR We are now looking for a Logic Design Engineer.As a member of our CPU Logic Design Team, you will be responsible for CPU on-chip interconnect network, coherency and last-level caches, focusing on such tasks as micro-architectural definition, RTL coding, logic debug, synthesis and timing closure, supporting verification and implementation. This position offers you the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.**What you'll be doing:*** As a member of our core CPU team, you'll own and be responsible for crafting and timely delivery of a specific unit on the chip.* Day to day tasks include: writing readable high performance and low power RTL, Synthesis and Timing closure, and design documentation.* Collaborate with our verification team to verify the correctness of your unit.* Work with implementation to achieve your timing, area, performance and power goals.* Assist with timing closure of super units.**What we need to see:*** Recent graduate with a BS or MS Degree in Electrical Engineering, Computer Engineering or Computer Science (or equivalent experience).* Experience in processor or other related high performance semiconductor designs.* Verilog expertise required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug* Effective communication and interpersonal skills are required along with the work in a dynamic, global team. Your successful track record of mentoring junior engineers and interns a huge plus.* A strong background in computer architecture***,*** cache coherency or high speed interconnects.NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the fastest and most power efficient chips in their class? If so, come join our CPU design team, we want to hear from you!Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 100,000 USD - 166,750 USD for Level 1, and 116,000 USD - 189,750 USD for Level 2.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until July 21, 2026.This posting is for an existing vacancy.NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.