ASIC Design Engineer - RTL, Verification, Timing & Mentoring

Job description

BayOne Solutions in Sunnyvale seeks an experienced RTL design engineer to translate functional specs into micro-architecture and implement high‑performance RTL using Verilog and SystemVerilog. You will develop functional coverage and SVA assertions, collaborate with the Verification team to identify corner-case bugs, and partner with the Physical Design team on timing closure.

The role includes mentoring new graduates and interns to cultivate design excellence.

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Worksite address

sunnyvale, CA, 94087, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.