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Job description
Company
Qualcomm Atheros, Inc.
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast‑paced Integrated Wireless Technology team you will be working with WiFi (802.11x) technology, SOC infrastructure, chip level verification and employ best‑in‑class Design and verification methodology.
Responsibilities
The candidate will be responsible for micro‑architecture, RTL design, and development of new functional blocks, as well as subsystem and full‑chip integration. This role is hands‑on and requires ownership of the design through the complete ASIC lifecycle, from concept through tape‑out. The candidate will collaborate closely with other subsystem teams to ensure smooth integration of releases, while interfacing with verification, DFT, FPGA emulation, and implementation teams.
Required Skills
5+ years of industry experience in ASIC design, micro‑architecture, and design integration
Strong background in SoC micro‑architecture, including specification, definition, and implementation of functional blocks
Hands‑on experience with multi‑domain clocking implementation in SOCs including understanding of clocking architectures, clock/power domain partitioning
Experience in Design linting and CDC analysis, including triage and closure of violations
Solid understanding of AMBA bus protocols, including AHB and APB
Proficiency in Python/Perl is required
Exposure to AI/ML based design methodologies is a strong plus
Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience
PhD in Science, Engineering, or related field
Preferred Skills
Experience with ARM CoreSight architecture and debug interfaces
Experience with AXI Bus protocol
Experience with PCIe and/or USB peripheral subsystems
Low Power design and implementation
Chip interconnect (NOC) implementation
Pay range and Other Compensation & Benefits
$126,700.00 - $190,100.00. The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants. In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play.
EEO Statement
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.