About this opportunity
Anysilicon lists this ASIC Implementation Engineer, Static Verification opportunity in sunnyvale, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
ASIC Implementation Engineer, Static Verification
Meta, 1180 Discovery Way, Sunnyvale, CA 94089
Job Description:
Meta is seeking experienced ASIC Frontend Implementation Engineers to join our Infrastructure organization. The ideal candidates will have a strong background in front-end implementation processes, from RTL to netlist, specifically for data center applications.
Responsibilities:
Perform Flat and Hierarchical Clock Domain Crossing (CDC) analysis and collaborate with designers for sign-off.
Conduct Flat and Hierarchical Reset Domain Crossing checks, working with Design and Firmware teams to develop reset groups and sequences.
Execute RTL Lint checks and collaborate with designers to create waivers.
Perform RTL Design for Test (DFT) analysis to enhance coverage for Stuck-at faults.
Run Logic/Physical Synthesis using advanced optimization techniques to generate optimized Gate Level Netlist for Timing, Area, and Power.
Develop automation scripts and methodologies for all Front-End tools, including Lint, CDC, and Reset Domain Crossing.
Collaborate with Design Engineers, DV Engineers, and Emulation Engineers to support handoff tasks and provide feedback to Physical Design Engineers regarding timing and congestion.
Qualifications:
Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.
6 years of experience with static verification tools.
Experience with Lint, Clock Domain, and Reset Domain crossing analysis.
Familiarity with SoC CDC signoff processes.
Knowledge of SoC integration aspects such as clocking, reset, and PLL.
Understanding of front-end ASIC flows.
Experience with RTL design using SystemVerilog or other Hardware Description Languages (HDLs).
Ability to communicate effectively across functional internal teams and with vendors.
Skills:
Experience with Netlist-CDC Analysis and improving Mean Time Between Failures (MTBF).
Proficiency in SoC Design Integration and Front-End Implementation.
Scripting and programming skills in Perl, Python, TCL, and Make.
Experience in developing structural rule-based checks for RTL and Netlist.
Knowledge of timing/physical libraries and SRAM memories.
Tell us what you're building and we'll recommend qualified vendors for your project.
ASIC Design Services
Verification
Packaging & Wafer
Semiconductor IP
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Tell us what you're building and we'll recommend qualified vendors for your project.
ASIC Design Services
Verification
Packaging & Wafer
Semiconductor IP
Work Email
Free No obligation Response within 24 hours
#J-18808-Ljbffr
Worksite address
sunnyvale, CA, 94087, US
Who can apply
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