About this opportunity
Anysilicon lists this ASIC Physical Design Engineer opportunity in los angeles, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
K2 is a pioneering space startup focused on developing the largest and highest-power satellites ever flown, backed by significant investment and contracts. The company aims to revolutionize satellite technology for missions ranging from Low Earth Orbit (LEO) to deep space, leveraging advancements in heavy-lift launch vehicles. K2 is seeking an ASIC Physical Design Engineer to contribute to the design of advanced System on Chips (SoCs) for next-generation satellite systems.
Responsibilities:
Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
Collaborate with DFT teams to ensure clean timing convergence.
Develop and maintain scripts and automation to improve flow efficiency and consistency.
Support physical sign-off activities including DRC/LVS, STA, EM, Signal Integrity, and power analysis.
Assist in chip-level integration, timing and functional ECOs, and tapeout preparation.
Contribute to methodology development, tool evaluation, and flow documentation.
Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
2+ years of experience in ASIC physical design for complex SoCs.
Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
Strong understanding of timing analysis, power optimization, and physical verification flows.
Experience with hierarchical or flat SoC design methodologies.
Familiarity with FinFET technologies.
Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.
Skills:
Exposure to radiation-hardened or space-qualified ASICs.
Experience with chip-package co-design or advanced packaging (2.5D/3D).
Familiarity with physical design service vendor management or offshore collaboration.
Experience with sign-off through TSMC.
Experience with Gate-All-Around technologies.
Experience working in cross-functional, geographically distributed teams.
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ASIC Design Services
Verification
Packaging & Wafer
Semiconductor IP
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Tell us what you're building and we'll recommend qualified vendors for your project.
ASIC Design Services
Verification
Packaging & Wafer
Semiconductor IP
Work Email
Free No obligation Response within 24 hours
#J-18808-Ljbffr
Worksite address
los angeles, CA, 90079, US
Who can apply
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