About this opportunity
WarmStart Ltd lists this ASIC Physical Design Engineer – Maynard, MA or Austin, TX opportunity in northern, Kentucky. Review the employer’s description below for duties, qualifications and application requirements.
Job description
ASIC Physical Design Engineer – Maynard, MA or Austin, TX
Cisco Systems, 12515 Research Blvd Bldg 4, Austin, TX 78759
Job Description:
Join the Cisco Acacia Communications team as a Physical Design Engineer, where you will contribute to the development of intelligent transceivers for high-speed fiber optic transmission. This role offers a unique blend of resources from a large organization and the dynamic culture of a smaller team, focusing on advanced semiconductor nodes.
Responsibilities:
Own and drive RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm).
Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
Implement and manage timing ECO strategies.
Collaborate closely with RTL and DFT designers to debug and root-cause physical implementation issues.
Evaluate and implement new timing methodologies; provide creative debugging solutions.
Contribute to best practices and drive methodology alignment across projects.
Qualifications:
Bachelor's degree in Computer or Electrical Engineering with 5+ years of experience, or a Master's degree with 3+ years of experience.
Hands-on experience in ASIC physical design and implementation.
Skills:
Experience with place & route using tools such as Cadence Innovus, Synopsys ICC2, or equivalent.
Familiarity with industry standard CAD methodologies (Cadence, Synopsys, or Mentor).
Experience with floor planning & partitioning, formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, EMIR.
Proficiency in Static Timing Analysis tools such as PrimeTime-DMSA or Tempus.
Scripting experience in languages such as TCL, Perl, or Python.
Synthesis experience with Synopsys DC/FC.
Formal Verification experience using tools like Synopsys Formality or Cadence LEC.
Experience with Power Integrity tools such as Apache Redhawk or Voltus.
Physical Verification DRC/LVS experience with tools like Synopsys ICV or Mentor Calibre.
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Who can apply
Review the original listing for work authorization, qualifications and employer requirements.