About this opportunity
Xcelerium lists this ASIC RTL Design Engineer: High-Performance SoCs & RISC-V opportunity in irvine, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Xcelerium, located in Irvine, CA, is seeking an ASIC RTL Design Engineer to develop high-performance, low-power digital designs and RISC-V cores. You will collaborate with various teams to optimize designs, ensuring quality and efficiency.
This role requires a Bachelor's degree in engineering and over 5 years of experience. A strong understanding of Verilog/SystemVerilog and a passion for technology will be essential for success in this innovative environment.
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Worksite address
irvine, CA, 92713, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.