Job description
About us
Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more responsive applications—whether in edge devices like drones, robotics, and sensors, or in cloud and data center environments. Our technology powers everything from large language models and CNNs to advanced signal processing, and is engineered to operate from –40 °C to +125 °C, making it ideal for industrial, automotive, aerospace, and defense.
We’ve raised over $100M from world-class investors including Softbank, Threshold Ventures, Lux Capital, and DCVC, and secured multi-million-dollar customer contracts across multiple markets.
About the role
Help push the boundaries of what can run on our accelerator. You’ll design compiler IRs and lowering strategies to support algorithmic workloads with irregular or dynamic control flow—loops, branches, and iterative methods—going beyond static neural networks. Working side by side with hardware engineers, you’ll influence ISA and execution model co-design to unlock new algorithm classes on analog and digital subsystems. The result: a compiler that makes complex algorithms practical to deploy while staying seamless for developers.
Here's what you will do
Extend compiler IRs to represent algorithms not easily captured in DNN graphs including control flow and iterative computation
Develop compilation strategies that unify analog compute with digital subsystems while maintaining performance and correctness
Prototype and optimize algorithms with irregular or dynamic control flow in compiler IRs, applying techniques such as vectorization, predication, and scheduling
Collaborate with hardware engineers to co-design ISA and features that improve support for algorithmic workloads
Define a roadmap for higher-level programming abstractions that simplify prototyping and accelerate deployment
Here's the background we hope you will have
3+ years of professional experience in compilers or high-performance systems software
Proficiency in modern C++ (C++14/17/20) and Python
Familiarity with compiler IRs (e.g., MLIR, LLVM, or equivalent) and their use representing complex program structures
Solid foundation in program analysis and optimization techniques (e.g., SSA form, loop optimizations, vectorization)
The following would be nice to have, but is not required
Hands-on experience developing MLIR or LLVM dialects for control flow (e.g. scf, cf) or affine/polyhedral representations.
Background in compiler-hardware co-design: working with hardware designers to refine ISA or execution models for efficiency
Proven ability to prototype irregular or control-flow algorithms in compiler IRs and optimize them for performance and resource constraints
Experience extending ML compiler stacks (ONNX, IREE, XLA, PyTorch, TVM) to support workloads beyond DNNs
What we offer
The opportunity to make algorithmic and control-flow-heavy workloads practical on novel accelerator hardware.
A role that bridges compiler design and hardware co-design, shaping both the IR and the accelerator architecture.
A collaborative, innovative team that values engineering rigor, continuous integration, and user-focused design.
Competitive compensation, equity, and benefits package.
At Mythic, we foster a collaborative and respectful environment where people can do their best work. We hire smart, capable individuals, provide the tools and support they need, and trust them to deliver. Our team brings a wide range of experiences and perspectives, which we see as a strength in solving hard problems together. We value professionalism, creativity, and integrity, and strive to make Mythic a place where every employee feels they belong and can contribute meaningfully.
Originally posted on Himalayas
Who can apply
Eligible countries: Canada, United States. Accepted UTC offsets: UTC-10, UTC-9, UTC-8, UTC-7, UTC-6, UTC-5, UTC-4, UTC-3.5, UTC+14. Review the full description for employer-specific work authorization, residency and schedule requirements.