About this opportunity
Cadence Design Systems lists this CPU Verification Director – Core & Memory Architect opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cadence Design Systems seeks a Design Verification Architect / Director to lead the Processor Verification team in San Jose, CA, and Austin, TX. You will verify microprocessor cores and peripherals, craft verification plans, and implement testbenches and coverage monitors for highly complex CPU designs.
The role requires 17+ years in design verification, strong leadership, and deep knowledge of SystemVerilog/UVM.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.