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Acceler8 Talent

Design Verification Engineer

mountain view, CA

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About this opportunity

Acceler8 Talent lists this Design Verification Engineer opportunity in mountain view, California. Review the employer’s description below for duties, qualifications and application requirements.

Job description

Design Verification Engineer

On-site | Mountain View, CA

$250k base + equity

I’m working with an AI compute startup rebuilding the hardware and software stack around extreme compute density.

The team is developing a tightly integrated platform spanning advanced silicon, packaging, firmware, compilers, kernels, and infrastructure. This role will own a major verification domain for its new AI accelerator, from planning through functional closure.

You’ll work closely with hardware and software teams, taking complex silicon from pre-silicon verification through first-silicon bring-up and scale-out.

You’ll work on problems such as:

Owning end-to-end verification for complex IP, subsystems, or full SoCs

Developing verification strategies from block level through SoC and emulation

Building UVM testbenches, test plans, coverage models, and reusable environments

Debugging complex functional failures and driving coverage closure

Verifying CPU subsystems, DMA, NoC, die-to-die interfaces, or multi-SoC systems

Using and developing AI-assisted flows to improve verification productivity

Partnering with architecture, RTL, firmware, and software teams

Looking for engineers who have:

5+ years of hands-on pre-silicon design-verification experience

End-to-end ownership from verification planning through functional closure

Strong SystemVerilog and UVM experience

Experience with block, subsystem, or full-chip verificationA track record of debugging complex IP or SoC designs

The ability to interpret specifications from both hardware and software perspectives

Experience defining clear milestones and delivering against aggressive silicon schedules

Nice to have:

CPU-subsystem or IP-integration verification

DMA, NoC, multi-chip, or die-to-die protocol verification

Palladium, Veloce, or similar emulation experience

Formal-verification experience

RISC-V knowledge

Post-silicon bring-up and debug experience

This is a senior individual-contributor opportunity with ownership of an entire verification domain for a new AI computing platform.

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Worksite address

mountain view, CA, 94039, US

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