About this opportunity
SPACE EXPLORATION TECHNOLOGIES CORP lists this DFT ASIC Engineer — RTL/Scan & ATPG opportunity in palo alto, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
SpaceX is seeking an ASIC/SOC DFT Engineer (Silicon Engineering) to develop cutting-edge ASICs for Starlink. You will work with cross-functional teams to design, verify, and implement scan insertion, DFT fabrics, and ATPG for high-reliability space systems.
The role requires a Bachelor’s in EE/CE/CS and 1+ years in ASICs, with experience in Verilog/SystemVerilog, UPF, and design-for-test workflows. Expect a highly dynamic, collaborative environment with long-term growth.
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Worksite address
palo alto, CA, 94306, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.