Digital ASIC Design Engineer II — RTL & SoC Impact

Job description

Microchip Technology Inc. in San Jose seeks an Engineer II to drive RTL implementation of digital IP blocks, focusing on power, performance, and area targets.

You will translate architectural concepts into SystemVerilog, work with SoC teams, and collaborate with Physical Design to resolve timing and routing challenges. The role requires 2.5–5 years in ASIC/FPGA digital design, a BS in Electrical Engineering, and proficiency in SystemVerilog and Cadence/Synopsys flows.

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Worksite address

san jose, CA, 95199, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.