About this opportunity
Gyga Force lists this Digital Design Engineer - ASIC opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Our client develops specialized semiconductor solutions for the edge, building processors capable of running AI workloads alongside bandwidth‑intensive sensors and wireless platforms. Their systems are designed to interpret and analyze RF data in ways that were not previously possible.
They are seeking a Senior SoC RTL Design Engineer to lead chip‑top RTL development and integration, ensuring that all IPs, subsystems, and hard macros come together cleanly in the final SoC. Responsibilities include RTL implementation, developing synthesis constraints, designing the I/O pad ring, evaluating power and thermal behavior, and working with physical design to support timing closure and overall system optimization.
This role requires strong experience in SoC architecture, RTL design, synthesis, timing, and physical implementation, and requires collaboration with DFT, PD, power/IR, and packaging teams.
RESPONSIBILITIES
Lead top‑level RTL development and integration, ensuring subsystems, IP blocks, and hard macros function correctly together.
Integrate internal and third‑party IPs, including processor cores, analog components, memory blocks, and interface peripherals.
Coordinate with subsystem owners to maintain a modular, synthesis‑friendly RTL structure.
Design the SoC pad ring and integrate major hard macros such as PLLs, PMUs, SRAMs, and PHYs.
Define high‑level strategies for power‑domain partitioning and ESD protection.
Establish SoC timing and synthesis constraints and work with physical design on floor planning and implementation.
Drive timing closure efforts and ensure reliable handling of clock‑domain crossings and reset schemes.
Support power integrity and thermal analysis in collaboration with PD and packaging teams, including IR‑drop mitigation and package‑level noise considerations.
Work with DFT engineering to integrate scan chains, BIST logic, and JTAG structures at the chip level.
Assist with test strategy validation and support post‑silicon bring‑up and debugging.
QUALIFICATIONS
7+ years of experience working on RTL design, integration, and SoC‑level implementation.
Strong background in SystemVerilog and hardware description languages for large, complex digital designs.
Experience assembling chip‑level components, including third‑party IPs, hard macros, and mixed‑signal interfaces.
Good understanding of clocking structures, clock‑domain and reset‑domain crossing concepts.
Hands‑on work with timing and synthesis constraints, static timing analysis, and closing timing on full‑chip designs.
Familiarity with major EDA tools used for synthesis, timing, and implementation (Design Compiler, Genus, PrimeTime, Tempus, etc.).
Ability to work with physical design teams on floor planning discussions and power/thermal considerations.
Understanding of power‑delivery networks, IR‑drop behavior, and basic package‑level limitations.
Exposure to DFT concepts such as scan, built‑in self‑test, and ATPG workflows.
Strong analytical and debugging skills, with the ability to collaborate across multiple engineering groups.
Degree in electrical engineering, computer engineering, computer science, or a related technical field (advanced degrees welcome).
INCENTIVES & BENEFITS
Equity
401(k) w/ 3% Match
Comprehensive medical, dental, vision, and life insurance
PTO and paid holidays
Relocation Assistance
H1B Visa Sponsorship (Transfers only)
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.