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Job description
Neuralink in California is seeking a Digital IC Design Engineer Intern to contribute to micro-architecture design and RTL implementation of low-power accelerators and SoC components for next-generation brain-computer interfaces.
You will collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team, tackling energy efficiency, performance, and verification challenges on silicon bring-up.
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Worksite address
south san francisco, CA, 94083, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.