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Job description
Astera Labs is seeking a Digital RTL Design Engineer focused on Static Timing Analysis for its San Jose design team. You will translate microarchitectural specs into synthesizable RTL and collaborate with verification, physical design, DFT, firmware, systems, and validation teams to ensure successful tapeout and silicon validation.
You will work on high-performance connectivity ASICs, contribute to timing closure, power optimization, and implementation flows, and help drive robust RTL quality
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.