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Job description
Apple is seeking a digital‑focused DV engineer to enable first silicon for IP designs in the San Francisco Bay Area. You will drive pre‑silicon verification, establish DV methodology, develop test plans and environments, and sign‑off for RTL tape‑out.
The role emphasizes SystemVerilog/UVM and scalable DV infrastructure for IP/SoC verification. Responsibilities include creating test plans, stress testing with SystemVerilog/UVM, debugging regressions, and using modern verification tools.
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Worksite address
san francisco, CA, 94199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.