About this opportunity
Ayar Labs lists this Director, Analog/Mixed-Signal Design opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Position: Director, Analog/Mixed‑Signal Design
Location: San Jose, CA
Job Id: 656
# of Openings: 0
Director, Analog/Mixed Signal Design
Location: San Jose, CA (on-site)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. We are hiring a Director of Analog/Mixed Signal Design to lead the team responsible for the advanced circuits at the heart of our optical I/O products. You will own the analog/mixed‑signal design strategy and execution for high‑bandwidth optical links, including high-speed transmit and receive signal paths, clocking, data conversion, biasing, and power‑management circuits. You will set clear technical direction, maintain a rigorous design methodology, and remove execution barriers, ensuring that the team delivers production‑quality silicon on schedule.
Key Responsibilities
Drive architectural decisions for the high-speed optical PHY of our next-generation product: TX path, RX path, clocking, and mixed‑signal control loops against a system‑level link budget shared with the photonics and laser teams.
Drive co‑design efforts across the EIC/PIC boundary.
Lead the silicon‑success methodology: first‑silicon‑success expectations, debug discipline, characterization-to-production.
Mentor AMS design engineers in design reviews and silicon debug.
Represent the AMS organization in cross‑functional architecture reviews, customer technical engagements, and foundry/EDA partner discussions.
Manage and scale the design team to develop IP intercepting multiple parallel products.
Basic Qualifications
B.S. in Electrical Engineering
12+ years of industry experience in analog/mixed signal design
Track record of production tapeouts in advanced FinFET CMOS nodes
Demonstrated ability to deliver complex analog/mixed‑signal IP across multiple concurrent programs.
Preferred Qualifications
M.S. or Ph.D in Electrical Engineering
Annual Salary Range: $240,000 - $300,000
Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.