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Job description
Hewlett Packard Enterprise is seeking an accomplished Director-level ASIC Design Leader to drive RTL implementation and tapeout readiness for next-generation networking ASICs. You will lead architecture-to-production efforts, align with architecture, verification, physical design, software, and product teams, and set standards for design quality and delivery.
In this role, you will shape technology strategy, manage multiple ASIC programs, and mentor senior engineers to build a high-performing,
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Worksite address
roseville, CA, 95678, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.