About this opportunity
Partcl lists this Founding Engineer (Systems + ML) opportunity in san francisco, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Join us to apply for the Founding Engineer (Systems + ML) role at Partcl .
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This range is provided by Partcl. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.
Base pay range
$130,000.00/yr - $200,000.00/yr
Responsibilities
Develop and optimize GPU‑accelerated engines (C++/CUDA) for timing analysis, gate‑sizing, place and route, synthesis.
Architect and build end‑to‑end pipelines: high‑performance kernels, efficient file IO, training models, latency-sensitive inference, CLI/UI layers.
Communicate with customers, deploy in their offices, fix production issues on the fly.
Partner with founders to shape product architecture and roadmap.
Required Skills
Proven experience shipping production C++ & GPU kernel code.
Experience designing, training, and deploying custom models (excluding GPT wrappers).
Deep understanding of systems: memory, latency, performance tradeoffs.
Versatility: comfortable toggling between model architecture design, low-level optimization, and scalable system design (N~>10M).
Fast learner: able to absorb EDA/physics concepts quickly.
Startup grit: thrive in ambiguity, iterate rapidly, debug complex issues.
Bonus: exposure to EDA, chip design, compilers, physics-driven ML.
You’ll be the first technical hire building products used at the core of next-generation chip design: tools that compress weeks-long flows into minutes, enabling real-time, AI-driven design loops. Partner with founders who’ve taped out chips, built rockets, and scaled GPU systems. Expect meaningful equity, deep technical challenges, and significant impact shaping the future of chip design.
To apply : Submit your application on YC’s WaaS platform. Highlight your experience with systems, GPU work, or ML, and tell us why Partcl matters to you.
No fluff. If you're ready to build the future of chip design, let’s talk.
Seniority level
Entry level
Employment type
Full-time
Job function
Information Technology
Industries
Technology, Information and Internet
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Worksite address
san francisco, CA, 94199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.