About this opportunity
Teradyne lists this FPGA & ASIC Compute Test Design Manager opportunity in reading, Massachusetts. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Teradyne North Reading is seeking an ASIC and Logic Design Engineering Manager to lead a 4–6 person FPGA/digital IP team. You will design and verify FPGA/ASIC components, collaborate with multiple engineering disciplines, and drive timely, high-quality deliverables for next-generation Compute Test products.
You will oversee staffing, planning, and budget, contribute to RTL code, and mentor engineers while coordinating with cross-functional teams to meet product requirements.
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Worksite address
reading, MA, 01814, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.