About this opportunity
Teradyne lists this FPGA/ASIC Methodology Engineer: Drive Design & Validation opportunity in reading, Massachusetts. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Teradyne in North Reading, MA seeks an ASIC/FPGA Methodology Engineer to define, develop, and maintain FPGA/ASIC design and verification workflows. Strong background in FPGA/embedded design and Linux-based tooling is essential for this role.
The candidate will optimize design flows for Vivado/Quartus, collaborate with design and verification teams, and contribute to CI/CD implementation using Jenkins, Docker, and Git. Excellent problem-solving and teamwork are required.
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Worksite address
reading, MA, 01814, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.