About this opportunity
Teradyne lists this FPGA & ASIC Verification Engineer - SystemVerilog/UVM opportunity in reading, Massachusetts. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Teradyne is seeking a Digital Logic Verification Engineer at our North Reading, MA center to focus on FPGA verification and related RTL work. You will collaborate with cross-functional teams to deliver robust designs, developing testbenches and UVM environments, and ensuring high coverage through systematic debugging and reviews.
The role requires 3+ years in digital logic verification, proficiency with SystemVerilog/UVM, and hands-on experience with Cadence Xcelium.
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Worksite address
reading, MA, 01814, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.