About this opportunity
Teradyne lists this FPGA Engineering Manager - Memory Test & RTL Lead opportunity in tualatin, Oregon. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Teradyne's Memory Test Division in Tualatin, OR is seeking an experienced FPGA Engineering Manager to lead a small team and deliver advanced memory test solutions, combining digital and analog design with PCIe, DDR, and SERDES interfaces.
You will plan multiple FPGA projects, mentor 4–6 engineers, collaborate across hardware, software, and firmware, and drive architectural reviews, RTL coding, and lab validation to ensure on-time delivery.
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Worksite address
tualatin, OR, 97062, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.