About this opportunity
Qualcomm lists this Hands-On Memory Subsystem Verification Engineer opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Qualcomm Technologies, Inc. is seeking a Design Verification Engineer to drive memory subsystem verification, including memory controllers, DDR/LPDDR/HBM interfaces, and PHY logic.
You will develop and execute verification strategies, build UVM-based testbenches, and write assertions, covering multiple modes and addressing complex verification challenges. The role requires strong Verilog/SystemVerilog/UVM skills, experience with constrained-random verification, and collaboration with RTL,
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.