About this opportunity
Vivid Technology lists this IC Packaging Engineer opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
This well-funded (Series B) start-up is building a new class of high-resolution perception sensing technology for ADAS and autonomous driving.
Seeking an IC Packaging Engineer to lead the development and delivery of advanced multi-chip packaging solutions for THz-system RFIC, SoC, and high-speed digital applications. This high-impact role combines technical leadership, hands‑on package design, and collaboration with OSATs, with a focus on 2.5D and interposer-based architectures. The ideal candidate will have deep expertise in package physical design (layout, stack‑ups, DFM, SI/PI), thermal‑mechanical modelling, and high-volume manufacturing and test, enabling them to execute designs directly or guide junior engineers toward production-ready solutions.
Responsibilities
Technical leadership, guiding the design and execution of advanced IC packages for multi-chip RFIC/SoC integration.
Develop 2.5D packages with UCIe chip‑to‑chip interconnects and interposer-based solutions.
Work on single‑sided and double‑sided RDL designs and on‑package RF antenna structures.
Co‑optimize package designs for signal integrity, power integrity, thermal, and mechanical performance in collaboration with RFIC, digital, and system engineers.
Drive material selection, DFM, and reliability qualification to meet automotive‑grade requirements (AEC‑Q).
Perform stress, warpage, and thermal simulations using tools such as ANSYS.
Maintain and leverage relationships with OSATs, substrate suppliers, and ecosystem partners to accelerate development.
Create and review electrical performance analysis (signal path length, PDN, crosstalk/noise etc.), mechanical analysis and drawings, stack‑ups, and layout constraints.
Lead failure analysis and root‑cause investigations for packaging and reliability issues and provide solutions to increase yield.
Contribute to the packaging roadmap and scalability plan for automotive volume production.
Key Qualifications
10+ years of experience in IC packaging design and development, including leadership responsibilities.
Proven track record with multi‑chip packages, digital + RF integration, and automotive applications.
Deep knowledge of UCIe interconnects, organic substrates, interposers, and advanced packaging architectures.
Experience with RF antenna integration in package designs.
Proficient in Flip‑Chip, Fan‑Out, 2.5D integration, and heterogeneous system‑in‑package solutions.
Strong understanding of packaging electrical performance such as signal and power integrity, mechanical stress, thermal management, and reliability analysis.
Established network with packaging vendors and OSATs.
M.S. or Ph.D. in Mechanical Engineering, Materials Science, Electrical Engineering, or related field.
Excellent communication skills and ability to thrive in a fast‑paced start‑up environment.
Why Join
Technical oversight, defining packaging solutions for breakthrough ADAS technology.
Collaborate with a world‑class engineering team spanning RFIC, SoC, and system design.
Be part of a well‑funded start‑up bringing innovative sensing technology to market.
Competitive compensation, stock options, and flexible work arrangements.
Location
Hybrid work from one of our offices in the Bay Area, CA.
Seniority level
Mid‑Senior level
Employment type
Full‑time
Job function
Engineering, Research, and Manufacturing
Industries
Semiconductor Manufacturing, Computer Hardware Manufacturing, and Motor Vehicle Manufacturing
Benefits
401(k)
Vision insurance
Medical insurance
Paid maternity leave
Paid paternity leave
Tuition assistance
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.