About this opportunity
Cadence Design Systems lists this Lead CPU Verification Architect — Equity Eligible opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cadence Design Systems seeks a Director of Design Verification to lead the Processor Verification team, overseeing verification of microprocessor cores and peripherals in a high-impact setting. The role requires deep DV expertise and strong leadership to guide 7–10 engineers.
Location includes San Jose, CA and Austin, TX, with a competitive salary and incentives. The ideal candidate will have 17+ years of verification experience, a BS in EE/CE, and mastery of SystemVerilog/UVM, assembly
#J-18808-Ljbffr
Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.