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Job description
Draper Laboratory in Cambridge, MA, seeks a Senior Digital ASIC Designer to implement high-performance digital ICs from RTL through synthesis.
Responsibilities include system-level design, optimization for performance and power, and leadership of multidisciplinary teams. Requires 7–10 years (or 5–10 with a Master’s) in ASIC hardware, with Cadence/Synopsys flows and SystemVerilog, Verilog or VHDL proficiency. On-site in Cambridge; US security clearance required.
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Worksite address
cambridge, MA, 02140, US
Who can apply
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