About this opportunity
Micron Technology lists this Lead DRAM RTL Design Engineer - PPA Mastery opportunity in boise, Idaho. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Micron Technology is seeking a Principal RTL Design Engineer to lead the RTL design lifecycle for DRAM IP, from architecture through signoff, at our Boise, Idaho site. You will drive high-performance, power- and area-efficient RTL solutions and partner with physical design, verification, and architecture teams to meet tight PPA targets.
The role requires strong Verilog/SystemVerilog skills, ASIC low-power experience (UPF), and a track record of pre-silicon RTL/IP ownership.
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Worksite address
boise, ID, 83708, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.