Job description
About Nearfield Instruments
Nearfield Instruments (NFI) is a fast-growing, high-tech scale-up. We design, develop, integrate, market, and service advanced metrology machines. Our solutions enable the world’s leading chipmakers to increase production yield and improve device performance—powering smaller, faster, and more energy-efficient electronics.
Nearfield brings together leading experts in science and engineering to develop a unique, high-throughput Scanning Probe Microscopy (SPM) platform delivering true 3D, sub-nanometer resolution metrology at production scale.
We are looking for a senior semiconductor expert with deep experience in hybrid bonding, chemical mechanical planarization (CMP), and advanced packaging, gained within a leading-edge fab, research institute, or semiconductor equipment company.
This expert will lead Nearfield Instruments’ application and technology direction for CMP, hybrid bonding, wafer-to-wafer and die-to-wafer integration, and advanced packaging. The role will identify the most critical process-control challenges, translate them into clear metrology requirements, and drive the development of new applications, capabilities, and product features that create greater value for customers.
Key responsibilities include:
Lead the identification of unmet metrology needs and critical process-control gaps in CMP, hybrid bonding, and advanced packaging.
Define the most valuable measurements, specifications, and use cases, including topography, dishing, erosion, surface roughness, edge roll-off, wafer shape, bonding interfaces, and full-die uniformity.
Set application priorities and translate customer and manufacturing needs into product and technology roadmaps.
Lead engagement with customers, process engineers, and equipment partners to validate requirements and accelerate adoption.
Drive the development of metrology solutions that improve yield, process stability, qualification time, and manufacturing performance.
Guide R&D and product teams on measurement performance, workflow integration, sampling strategies, and high-volume manufacturing requirements.
The ideal candidate has:
Significant experience in semiconductor process integration, CMP, hybrid bonding, or advanced packaging.
Strong understanding of metrology, inspection, and process control in high-volume manufacturing.
Experience working with leading semiconductor fabs, equipment suppliers, or advanced R&D organizations.
A proven ability to lead cross-functional teams and convert complex process challenges into differentiated products and applications
Originally posted on Himalayas
Who can apply
Eligible countries: China, Germany, Japan, South Korea, Taiwan, United States. Accepted UTC offsets: UTC-10, UTC-9, UTC-8, UTC-7, UTC-6, UTC-5, UTC+1, UTC+6, UTC+8, UTC+9, UTC+14. Review the full description for employer-specific work authorization, residency and schedule requirements.