About this opportunity
CScale lists this Lead FEA Packaging Engineer – Optical ICs opportunity in palo alto, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cspeed IO in Palo Alto seeks an experienced FEA engineer to drive thermal and structural analysis for optical engine packages. You will build and validate models that influence architecture decisions and qualification, with close collaboration across design, packaging, and suppliers.
The role requires a PhD or MS in engineering, 6+ years of semiconductor packaging FEA, and proficiency in one major FEA/CFD tool plus a second for the complementary domain; experience with 2.5D/3D integration and
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Worksite address
palo alto, CA, 94306, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.