About this opportunity
Teradyne lists this Lead FPGA & ASIC Design Manager, Compute Test opportunity in north reading, Massachusetts. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Teradyne in North Reading, MA, seeks an ASIC and Logic Design Engineering Manager to lead a 4–6 person FPGA/ASIC team for Compute Test products. You will oversee 2–3 FPGA/digital IP projects, collaborate across disciplines, and ensure timely deliverables in budget.
The role requires RTL coding, strong leadership, and experience with Vivado/Quartus, Cadence, clocking constraints, and high‑volume hardware development. Excellent communication skills are essential.
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Worksite address
north reading, MA, 01864, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.