About this opportunity
Celero Communications, Inc. lists this Lead High-Speed Analog Layout Architect opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Celero Communications, Inc. is seeking a Principal High-Speed Analog Layout Design Engineer in San Jose, CA to drive layout of analog/mixed-signal IP blocks for state-of-the-art optical communication systems.
You will lead floor planning, collaborate with schematic designers, mentor junior engineers, and ensure first-pass silicon success through rigorous LVS/DRC/PERC checks and advanced layout techniques.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.