About this opportunity
Cadence lists this Lead Processor Verification Architect opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cadence is seeking a Design Verification Team Director in California or Austin to lead the Processor Verification team. You will verify microprocessor cores and peripherals, craft verification plans, and implement testbenches with coverage closure.
You will coordinate with DV/Arch/Design/FW teams and report on a 7-10 engineer group. The role demands 17+ years in design verification, a BS in EE/CE, strong leadership, and deep knowledge of SystemVerilog/UVM, plus scripting skills (Perl/Unix
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.