About this opportunity
Cadence Design Systems lists this Lead Software Engineer: Low-Power Verification (Equity) opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cadence Design Systems in San Jose is seeking a Lead Software Engineer to advance low-power verification software for Palladium and Protium platforms. You will improve UPF compilation performance, add support for new IEEE 1801 LRM revisions, and document end-to-end workflows with SystemVerilog and UPF examples.
You will work with R&D, PE and AE teams to deploy UPF solutions across key flows (AVIP, UVMA, MC, Dielets) and ensure code and docs stay in sync through example-driven checks.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.