About this opportunity
Cadence Design Systems lists this Lead Software Engineer - Low-Power Verification (UPF) opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cadence Design Systems in California is seeking a Lead Software Engineer - Low Power Verification to advance UPF debug features and RTL support as part of Palladium and Protium flows.
You will enhance UPF performance, scale event logging for multi-billion-gate designs, and help document end-to-end workflows with SystemVerilog and UPF examples. Collaboration across R&D, PE and AE teams is required, with a focus on high-quality, scalable software.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.