About this opportunity
Renesas Electronics Corp. lists this Lead SystemVerilog/UVM Verification Architect – DDR6 opportunity in plano, Texas. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Renesas Electronics Corp. in Plano, TX is seeking a Principal Design Verification Engineer to lead verification strategy and execution for next‑generation memory interface products, including data buffers and DDR IP.
You will own verification of complex digital designs at the block and system levels, collaborating with RTL/design engineers to ensure quality and sign‑off. The ideal candidate has deep SystemVerilog and UVM experience, strong technical leadership, and a track record of driving
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Worksite address
plano, TX, 75086, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.