About this opportunity
Achronix Semiconductor Corporation lists this Lead Test Development Engineer opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.
Job Description/Responsibilities
Achronix is seeking a motivated experienced Lead Test Development Engineer to join the Hardware Engineering team. In this role, you will lead the definition and implementation of manufacturing test solutions, developing production, characterization, and qualification test programs to ensure reliable, high-performance products for Achronix’s portfolio of FPGAs. You will work with design, product, and operation teams to enhance test coverage, optimize test time, and deliver solutions from early silicon bring-up to high-volume manufacturing. We are looking for candidates in the range of Sr. Staff Engineer to Sr. Principle Engineer levels.
DFT Architecture and Implementation Define and implement DFT architecture , including scan, boundary scan (IEEE 1149.1/1687), MBIST , and related features.
Collaborate with design and physical design teams to ensure integration and thorough verification of DFT features at RTL and gate levels.
Design and implement test mode controls and access mechanisms to support effective testing and verification.
Test Generation and Simulation Generate and validate ATPG patterns for stuck-at, transition delay, and path delay faults .
Generate test cases targeting specific FPGA blocks and IP, including reconfigurable core fabric logic, DSPs, and embedded memories.
Work with internal and third-party IP vendors to integrate testing solutions for external memory interfaces (DDR5, GDDR6), and high-speed I/O interfaces (SerDes, PCIe, Ethernet).
Perform fault coverage analysis and implement improvements.
Conduct gate-level simulations with test patterns to verify correctness and ensure timing closure.
Silicon Bring-Up and ATE Support Perform silicon test pattern bring-up, validation, and debugging on lab bench and ATE platforms.
Implement and debug scan , BIST , and functional tests on production testers.
Conduct a comprehensive analysis of yield issues and correlate silicon data with design and DFT logic.
Automation and Scripting Develop and maintain scripts in Python , Perl, or Tcl to automate pattern generation, simulation, data analysis, and test vector conversion to ATE format.
Maintain and improve internal DFT and test infrastructure workflows.
Cross-Functional Collaboration Work with design, verification, product engineering, and manufacturing teams to ensure testability and deliver high-quality silicon.
Required Skills/Experience
Have 10+ years of experience in DFT, testing, or silicon validation.
Demonstrate a solid understanding of scan insertion, ATPG, MBIST, and fault models.
Be experienced with Synopsys TestMax, Siemens Tessent , and similar DFT EDA tools.
Demonstrate proficiency with JTAG, boundary scan, and related IEEE standards such as 1149.1 and 1149.6.
Have hands-on experience with ATPG, MBIST and functional pattern generation, simulation, and verification.
Be familiar with script-based test case generators and understand industry-standard test pattern formats such as WGL and STIL .
Be proficient in scripting languages, including Python, Perl, or Tcl.
Demonstrate strong debugging and problem-solving skills for silicon and test issues.
Preferred Skills
Be familiar with ATE test program development and debugging (Advantest 93K), silicon bring-up, and volume production testing.
Possess knowledge of silicon yield analysis, failure diagnosis, and reliability testing.
Understand DFT implications for physical design, including scan chain reordering and test mode timing.
Experience with FPGA design and architecture is a plus.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.