Lead VLSI Physical Design Engineer – RTL to GDSII

Job description

VLSI Worlds in Folsom, CA is seeking a Senior Physical Design Engineer for ASIC/SoC projects. You will lead block-level physical design from RTL to GDSII, ensuring timing, power, and area targets are met on advanced nodes.

The role requires 10+ years of relevant experience and hands-on Fusion Compiler expertise. You will collaborate with RTL, EDA, and tape-out teams to deliver silicon on schedule.

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Worksite address

folsom, CA, 95630, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.