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Job description
Neuralink seeks experienced engineers for a Digital IC Design Engineer Intern role focused on next-generation chip architectures and hardware accelerators. You will collaborate with chip designers, electrical engineers, algorithms engineers, and software engineers on a compact, agile team to push the boundaries of energy efficiency and silicon technology.
The position emphasizes hands-on RTL, micro-architecture, and verification work, with opportunities to influence silicon bring-up and test
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Worksite address
south san francisco, CA, 94083, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.