About this opportunity
NVIDIA Corporation lists this NVIDIA ASIC Physical Design Engineer New Grad - Netlisting · Austin, TX, Santa Clara, CA ASIC Physical Design Engineer New Grad - Netlisting New Grad Austin, TX, Santa Clara, CA 3mo ago opportunity in northern, Kentucky. Review the employer’s description below for duties, qualifications and application requirements.
Job description
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for a motivated ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.
What you’ll be doing:
Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.
Help in ECO generation and implementation.
What we need to see:
Master's or PhD degree in Electrical or Computer Engineering (or equivalent experience).
Shown knowledge in logic equivalence checking/Formal Verification required from RTL to tapeout with industry-standard tools.
Understanding of hardware architecture and hands-on skills in RTL/logic design for timing closure.
Experience in clock-domain-crossing checking, MTBF analysis, either with EDA tools (i.e., Synopsys or Cadence) or in-house tools.
Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.
In-depth knowledge of industry standard EDA tools in related fields.
Experience in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.
Ways to stand out from the crowd:
Experience in logic synthesis and equivalence checking/FV.
Familiarity with industry tools and flow.
Strong hands-on debugging capability and problem-solving skills.
Experience improving workflows and productivity through effective AI utilization is a plus.
Salary
The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3. You will also be eligible for equity and benefits.
Application Deadline
Applications for this job will be accepted at least until August 17, 2026.
Equal Opportunity
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Who can apply
Review the original listing for work authorization, qualifications and employer requirements.