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Job description
Optical Reliability Sr Staff/Principal Engineer
Category: Chip Design
Location: San Jose, CA
Experience: More than 8 Years Work Expe.
Job Description
Reliability Strategy & DfR: Partner closely with PIC (Photonic Integrated Circuit), component, and assembly design teams early in development to implement Design for Reliability (DfR) principles.
Risk Assessment: Lead FMEA (Failure Mode and Effects Analysis) and DFMEA sessions with cross-functional groups to proactively flag and mitigate potential product failure points.
Qualification & Standards: Author and execute comprehensive product qualification plans at the component, assembly, and module levels, ensuring strict compliance with GR-468 (Telcordia) and JEDEC industrial testing standards.
Advanced Reliability Modeling: Develop and execute accelerated life test strategies, including Reliability lifetime Modeling, activation energy (Ea) extraction, and use-condition acceleration metrics to extrapolate product reliability boundaries.
Packaging Reliability: Define and model the Reliability Failure Modes of Silicon / Packaging technologies, specifically targeting challenges in 2.5D / 3D packaging, Multi-Chip-Modules, and high-density optoelectronic interfaces.
Statistical Data Analysis: Utilize statistical tools like JMP to analyze process, qualification, and degradation data to maintain product FIT (Failures in Time) and MTBF estimates.
Failure Analysis & Customer Operations: Lead complex root-cause failure analysis (FA) for qualification drop-outs and field returns (RMA), driving robust 8D corrective actions.
Ecosystem Management: Oversee qualification execution and scale quality control structures directly with global OSAT partners and contract manufacturers (CM).
Main Requirements and Qualifications
Education: Master's or Ph.D. in Electrical Engineering, Materials Science, Physics, or a related engineering field.
Experience: 8+ years of hands‑on experience in product quality, qualification, and reliability engineering specializing in optoelectronic hardware.
Domain Expertise: Strong engineering background in semiconductor optical devices, including III‑V platforms (e.g., InP, InGaAs), Silicon Photonic platforms, and directly modulated Micro-LED (GaN) architectures.
Packaging Mastery: Proficient understanding of physics-of-failure modes tied to high-density sub‑assemblies, Multi-Chip-Modules, and 2.5D / 3D packaging schemes.
Data Command: Expert-level capability utilizing JMP for statistical analysis, Weibull math, and life-data distributions.
Standards Knowledge: In-depth familiarity with accelerated stress environments (HTOL, HAST, ESD/LU) rooted specifically in GR-468 benchmarks.
Salary range: $188,000- $301,000
Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more.
MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.