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Job description
Micron Technology is seeking a Principal ASIC Design Engineer to lead digital RTL design, synthesis, and timing closure across a front-to-back ASIC flow. You will own block architecture, CDC strategies, and the interface with layout.
Collaboration with verification, GLS, and lab bring-up teams will be essential. Your experience should include a complete tape-out and proficiency with Design Compiler/Genus, PrimeTime/Tempus, VCS/Xcelium, and DFT methods.
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Worksite address
folsom, CA, 95630, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.