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Job description
Yoh, a Day & Zimmermann company, is seeking a Principal ASIC Design Engineer to own front-end design for complex, high-performance networking silicon used in AI infrastructure.
The role demands hands-on RTL development, multiple tapeouts, and close collaboration with architecture, verification, emulation, DFT, and physical design teams to translate product requirements into robust microarchitecture and production-ready RTL.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.