About this opportunity
Anysilicon lists this Principal ASIC Engineer, Annapurna Labs opportunity in cupertino, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Job Description:
Amazon Web Services (AWS) is seeking experienced Physical Design Engineers to join the Silicon Optimization Engineering Team, responsible for designing and optimizing hardware for AWS data centers. This role involves leveraging new technologies to enhance large-scale deployments, ensuring a world-class customer experience in a fast-paced environment.
Responsibilities:
Collaborate with RTL/logic designers to conduct architectural feasibility studies and assess power-performance-area tradeoffs for physical design closure.
Drive block physical implementation processes including synthesis, formal verification, floor planning, bus/pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification, ECO, and sign-off.
Develop and refine physical design methodologies.
Evaluate third-party IP and provide recommendations based on findings.
Foster collaboration and teamwork with other physical design engineers and RTL/Architecture teams.
Qualifications:
Bachelor's degree with 12+ years of experience or Master's degree with 8+ years in Electrical Engineering or Computer Science.
6+ years of experience in ASIC Physical Design from RTL to GDSII in technologies such as 7nm, 14/16nm, 20nm, or 28nm.
Proficiency in CAD tools (e.g., Cadence, Mentor Graphics, Synopsys) for various physical design tasks.
Scripting experience in Tcl, Perl, or Python.
Skills:
Expertise in physical design flows including synthesis, formal verification, floor planning, and timing closure.
Strong knowledge of device physics and custom/semi-custom implementation techniques.
Experience in integrating IP and specifying IP requirements in the physical domain.
Ability to solve physical design challenges across various technologies like DDR and PCIe.
Mentorship skills to guide junior engineers and foster effective teamwork.
Tell us what you're building and we'll recommend qualified vendors for your project.
ASIC Design Services
Verification
Packaging & Wafer
Semiconductor IP
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Tell us what you're building and we'll recommend qualified vendors for your project.
ASIC Design Services
Verification
Packaging & Wafer
Semiconductor IP
Work Email
Free No obligation Response within 24 hours
#J-18808-Ljbffr
Worksite address
cupertino, CA, 95014, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.