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Job description
Jariet Technologies, Inc. is seeking a principal ASIC functional verification engineer to design and implement verification test benches for high-speed digital SoCs.
The role may involve team leadership and close collaboration with the VLSI Design team to define verification strategies and plans. Ideal candidates will have extensive SystemVerilog/UVM experience, coverage methodology expertise, and strong written and verbal communication skills.
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Worksite address
aliso viejo, CA, 92656, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.