About this opportunity
Celero Communications, Inc. lists this Principal Physical Design Engineer opportunity in irvine, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Principal Physical Design Engineer
RTL-to-GDSII Execution: Own physical implementation of System-on-Chips (SoCs) or complex digital blocks.
Design Optimization: Manage floor-planning, bump planning, power grid design, and clock tree synthesis (CTS) to optimize chip performance.
Design Convergence: Resolve timing, congestions, EM/IR issues together with Frontend Designers
Signoff & Verification: Run Static Timing Analysis (STA) and physical verification. Fix Design Rule Checking (DRC) and Layout Versus Schematic (LVS) violations.
Methodology Development: Drive automation and improve flow robustness using scripting languages like Tcl, Python, or Perl.
Cross-Functional Leadership: Partner with architects, logic designers, and analog design team for tapeout readiness.
Key Qualifications
Experience: 7+ to 15+ years of relevant ASIC physical design experience (depending on degree level).
Process Knowledge: Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm).
Tool Mastery: Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, , Tempus, Voltus, Pegasus, Calibre).
Technical Concepts: Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup.
Annual Base Salary Range: $200,000 to $300,000 (The final offer will be determined based on job-related skills, experience, qualifications, and location.)
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Worksite address
irvine, CA, 92713, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.